JEDEC DDR4 JESD79-4 STANDARD

The JEDEC DDR4 JESD79-4 standard will span memory speeds from DDR4-1600 to DDR4-3200. One change in the design of the DIMM is the slight circular edge which is intended to make insertion substantially easier than with easier designs.

  • 1.2V operation
  • DDR4-1600 to DDR4-3200
  • 4, 8 and 16 gigabit dies
  • 2GB, 4GB, 8GB, 16GB and 32GB DIMMs

DDR4 offers a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. In addition to the advantages described later in this release, the new technology has been defined with a goal of simplifying migration and enabling adoption of an industry-wide standard.

The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a gear down mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The DDR4 architecture is an 8n prefetch with two or four selectable bank groups.  This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. 

In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load. Servers have long needed more RAM to handle heavy workloads. In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to seven (128 possible banks).