THE FUNDAMENTAL LIMIT OF SILICON

Much as the marketing department at TSMC and Intel would have you believe the number of transistors per square millimeter is not going to be markedly increased. The reason is that the atomic size of silicon is 110 pm. So given one layer of silicon to make a gate work will be the engineering feat of all time. Hafnium has been used to reduce gate leakage starting at 45nm.

The atomic size of silicon in the ingot is 110-120 pm apart. This is why there is a limit to the industry, Instead the industry will have to rethink the design of devices and products. Already the industry is adopting the chiplet approach mostly to improve yields s larger devices tend to have excessive defect rate,

At present a few atoms thick gates are needed to make a FET functional. Even at the smallest scales there is a limit to how thin the gate can get. The same idea applies to the source and the drain with the FET. The fundamental requirements of silicon cannot be ignored.

While the limits are well established there is still some room for the industry to move towards 2000 pm wich is now down in the realm of atomic physics. It’s unlikely transistors will function well at 2000 pm due to extreme quantum effects. Quantum effects will also affect the FET design.

Quantum effects have been observed, studied and theorized for years, and not just in the semiconductor industry. Quantum tunneling, for example, has been documented for nearly a century in alpha particle decay research. But in the chip world, these quantum effects show up in a variety of strange behaviors that are becoming increasingly problematic.

As designs shrink to below 10 nm and beyond, quantum effects are emerging as a more widespread and significant problem, and one that ultimately will affect everyone working at those nodes. At smaller sizes the quantum effects are significantly higher.

Some work is ongoing to purify 28Si from the troublesome 29Si. Evidently the quantum effects are reduced when the 29Si is removed. Of course making isotopic pure silicon will be extremely hard to do.

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