AMD is developing Zen 3 for the next gen socket AM5 which will herald the migration to DDR5,

The bus on the CCX design of Zen 2 is now redesigned as a mech architecture. The change is intended to improve the communcations between components. The bidirectional ring topology is designed to reduce latency.

Intel realized in the early 2010s that it could not scale up CPU core counts on its monolithic processor dies beyond a point using Ring Bus, and had to innovate the Mesh Topology. The Mesh is a more advanced ringbus but with additional points of connectivity between components, making halfway between a Ring Bus and full-interconnectivity (in which each component is directly interconnected with the other, an impractical solution at scale).


A earlier leak from Gigabyte showed a block daigram for the first gen DDR5 systems. The idea that AMD would make all processors graphics capable suggests a good move as long as the PCIe lanes are not permanently assigned.

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