PCI EXPRESS 6.0 WORK CONTINUES

The upcoming PCIe 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets. Once the link operates in FLIT mode, any speed change to lower data rates will also have to use the same FLIT mode. Once enabled, FLIT mode is followed in the link, regardless of the speed. The improved bandwidth that results from low overhead amortization allows for high bandwidth efficiency, low latency and reduced area.

The PCIe 6.0 specification also introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Forward Error Correction (FEC), allowing the PCIe 6.0 specification to achieve low latency, low complexity, and a low bandwidth overhead.

Each FLIT is protected by a Cyclic Redundancy Check (CRC) and a 3-way interleaved FEC. After a FLIT is received, the receiving device performs the FEC decode, which corrects any correctable error within each FEC group. After the decode, the CRC check is performed. If the CRC check fails, the receiving device can indicate that the FLIT has not been successfully received by sending a NAK (no acknowledgment) back to the transmitting device. The NAK causes a replay, resulting in the FLIT being replayed and delivered without any errors. An optimization is possible if the subsequent FLIT indicates that the FLIT in error had only No Operation (NOP) transaction layer packets, which makes the replay unnecessary.

“Failure in Time” (FIT) is a metric used to measure reliability or the failure rate. It is the number of “failures” we get in 109 hours. A failure is defined when the CRC passes even in the presence of bit error(s), resulting in potential data integrity issues. This is the reason why we have always deployed a strong CRC with very low aliasing probability, even in the presence of multiple errors. In the context of Flit, if an erroneous FLIT, even after the FEC correction, remains erroneous and the subsequent CRC check still passes (i.e. the CRC fails to recognize the error, “aliasing” in signature to a correct code), it is considered a failure. We want the FIT to be significantly less than 1 for any link width. Our analysis shows that we expect the FIT to be around 5 x 10-10, which is almost 0. In that regard, PCIe 6.0 specification is a very robust interconnect, as the prior generations.

The PCI SIG has worked to make PCIe 6.0 the best it can be within the realms of technological capabilities. Layers of ECC are reducing error rate to be very low so that data integrity is sound.

At present SSD products have the lowest error rates followed by tape. Hard disks are competitive for low error rates as well. All the storage technology vendors use ECC to reduce error rates to very low rates.

Video card vendors have not yet make it to PCIe 5.0 speeds yet as there is not that much need for bandwidth even with AMD Smart Access Memory. As memory management improves gaming cards will be able to use the PCIe to handle faster memory.